1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the same, and more particularly relates to a dynamic random access memory that is a semiconductor memory with capacitors and a method of manufacturing the same.
2. Description of Related Art
A dynamic random access memory (hereafter, referred to as DRAM) of a semiconductor memory is provided with single cell transistor 211 and single capacitor 221, as shown in FIG. 11A. A gate of the cell transistor 211 is connected to a word line 231. Further, one diffusion layer of the cell transistor is connected to a bit line 241, and the other diffusion layer of the cell transistor 211 is connected to one electrode of the capacitor 221. Furthermore, the other electrode of the capacitor is connected to a plate electrode.
A memory cell of single-transistor-single-capacitor type having the above mentioned configuration is widely used since it has an advantage over other memory devices in achieving a higher degree of integration. However, there is always demands for even higher degree of integration in DRAM. Enormous efforts have been tried to advance miniaturization of such memory cells.
As a typical DRAM cell, a stack type capacitor cell and a trench type capacitor cell have been put to practical use until now. However, in order to form the memory cells of these types, it is inevitable that their structures become more complex if further reduction of cell area is attempted.
The DRAM memory comprises: a capacitor for accumulating memory charge, a transistor for receiving and outputting the charge, a bit line that is connected to the transistor for writing and reading data, and a word line to control on/off switch action of the transistor. In the DRAM memory cell, major development effort has been spent on how to reduce its cell size.
The reduction of the cell size while maintaining a required amount of the charge to be accumulated in the capacitor of the cell is one of most important issues of the development. Instead of a memory cell in which a capacitor is formed in a flat layout referred to as a planer type, the above mentioned cell structures such as the trench type, the stack type or the like are employed to make the capacitor structure three-dimensional in order to increasing the amount of charging capacitance within a smaller area size. Furthermore, as a material having a higher dielectric constant, for example, tantalum oxide (Ta2O5) and the like are used as an insulation film of the capacitor.
It is popular to use memory cells configured with a folded bit line system as shown in FIG. 11B. Such memory cells have been known to share a higher noise resistance characteristic found in conventional cell read-out operation. However, it is also known that the minimum memory cell area can not be less than 8F2 in such memory cell if the minimum machining dimension is assumed to be F. In order to attain less memory cell size, it is desirable to employ a layout configuration referred to as an open bit line system. FIGS. 11B, 11C show connection diagrams of the memory cells having configurations of the folded bit line system and the open bit line system, respectively.
As shown in FIG. 11, in memory cells with the folded bit line system, memory cells 201, each of which comprises the cell transistor 211 and the capacitor 221, are arranged so as to be connected to every other line of the word lines 231 between the bit lines 241. Further, the memory cells 201 are arranged so as to be connected to every other line of the bit lines 241 between word lines 231.
As shown in FIG. 11C, in memory cells with the open bit line system, the memory cell comprises the cell transistor 211 and the capacitor 221 and arranged so as to be connected to each word line 231 between the bit lines 241.